The increasing of the semiconductor device's integration necessitates the shrinkage of the channel length of the MOS device. Accordingly a dropped threshold voltage Vt and a short channel effect which will adversely influence the control of the MOS device by the gate voltage Vg thus take place. In addition, since the channel near the drain has increased carriers, an electrical breakdown is therefore occurred. A hot electron effect caused by the electrical breakdown accordingly happens, and thus the normal function of the MOS device is strongly influenced by the abovementioned phenomena.
Basically, the lightly doped drain (LDD) is a preferred method adopted to solve the hot electron effects. In executing the LDD, the density of the doped dopant on the regions nearby the source and the drain is reduced in order to solve therefor the electrical breakdown effect caused by the multiplied carriers occurred at the channel near to the source and the drain.
However, as is well known, the disadvantage of the LDD is the complexity resulting from the needed processes, and thus if it is further to be employed by the complex process of fabricating the CMOS device, the sophistication encountered in the involved fabricating process is therefore aggravated.
The entire procedure for manufacturing a CMOS device includes from the beginning process of forming the gate to the final process of accomplishing the source and the drain according to the conventional method. A process for fabricating a CMOS device having twin tubs is exemplarily illustrated as follows:
The CMOS device having therein an active area, a field oxide and a silicon substrate. The active area further includes a gate oxide, and a gate conducting layer is overlapped upon the field oxide and the gate oxide. The active area is utilized to form at least a p-type and an n-type MOS regions. The conventional method used for manufacturing the CMOS device containing the processes for forming a gate, the source and the drain generally includes the following steps:
(a) employing a photolithography and an etching technique to remove a portion of the gate conducting layer in order to respectively define a first and a second gate areas on the p-type and the n-type MOS regions; PA1 (b) utilizing a photolithography and an etching technique to form a first photoresist mask over one of the p-type and the n-type MOS regions and executing a first ion implantation in order to form a first lightly doped drain (LDD) upon the other one of the p-type and the n-type MOS regions; PA1 (c) eliminating the first photoresist mask; PA1 (d) using a photolithography and an etching technique for forming a second photoresist mask over the other one of the p-type and the n-type MOS regions and performing a second ion implantation in order to form a second lightly doped drain (LDD) upon one of the p-type and the n-type MOS regions; PA1 (e) removing the second photoresist mask; PA1 (f) utilizing a chemical vapor deposition (CVD) for forming a dielectric layer upon the p-type and the n-type MOS regions; PA1 (g) employing an anisotropic dry etching for removing a portion of the dielectric layer in order to respectively form a first and a second gate sidewalls upon the first and the second gate; PA1 (h) utilizing a photolithography and an etching technique to form a third photoresist mask over the other one of the p-type and the n-type MOS regions and executing a third ion implantation in order to form thereon heavy doped first source and first drain; PA1 (i) removing the third photoresist mask; PA1 (j) using a photolithography and an etching technique to form a fourth photoresist mask on one of the p-type and the n-type MOS regions and performing a fourth ion implantation in order to form thereon heavy doped second source and second drain; and PA1 (k) eliminating the fourth photoresist mask.
According to the above descriptions, the conventional method employed for manufacturing the CMOS device includes the beginning process of forming the gate, the LDD process executed for eliminating the hot electron effects, and the final process of forming the source and the drain, in which at least five photolithography and etching processes are required for accomplishing the work. However, for eliminating the hot electron effects in order to promote the performance of the CMOS device, the process for executing the LDD is therefore unavoidable. Hence, how to reduce the number of the steps in performing the method for manufacturing the CMOS device is therefore a real challenge to all relevant researchers.
Accordingly, the most important factor which affects the consumed time and cost during the period of manufacturing the CMOS device is the needed photolithography and the etching process. Hence, if the number of the processes of the photolithography and the etching technique can be reduced and the performance promotion of the CMOS device can still be obtained, then the time and the cost consumed in the manufacturing process are thus decreased. Therefore, achieving the above mentioned advantages explains why the present invention is thus invented.